Switching regulator and control device therefor

ABSTRACT

A control device serves as an agent that controls a switching regulator including an output switch and a synchronous rectification switch. The control device includes: a summator generating a sum sense signal by adding up a first sense signal commensurate with the current passing in the output switch and a second sense signal commensurate with the current passing in the synchronous rectification switch; a smoother generating a smoothed sense signal by smoothing the sum sense signal; and a switch driver driving the output switch and the synchronous rectification switch complementarily through current mode control based on the smoothed sense signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the following Japanese Patent Applications,and their contents are hereby incorporated by reference:

-   -   (1) Japanese Patent Application published as No. 2017-022370        (filed on Feb. 9, 2017)    -   (2) Japanese Patent Application published as No. 2017-246421        (filed on Dec. 22, 2017)

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a current mode control switchingregulator. More particularly, the present invention relates to a currentmode control switching regulator that can eliminate the influence ofringing noise that occurs when a high-side and a low-side transistorturn ON and OFF.

2. Description of Related Art

Some conventional current mode control switching regulators achievecurrent mode control by sensing a current passing in at least one of alow-side and a high-side transistor.

Japanese Patent Application published as No. 2016-67113 (hereinafter“Patent Document 1”) proposes current mode control switching powersupplies. Patent Document 1 discloses, in FIG. 1, one that senses thecurrent passing in the low-side transistor, in FIG. 14, one that sensesthe current passing in the high-side transistor, and in FIG. 11, onethat senses the currents passing in both transistors.

Japanese Patent Application published as No. 2011-135629 (hereinafter“Patent Document 2”) discloses a motor control device capable of currentsensing without the influence of ringing noise. This type of motorcontrol device is provided with a current sensor that senses orestimates the value of the current that passes in a connection circuitfor a brushless motor in the ON period in which whichever of an upperarm switch (high-side transistor) and a lower arm switch (low-sidetransistor) has the higher duty factor is ON.

Patent Document 2 teaches, in paragraph 0020 (Embodiment 3), an examplewhere the motor current is monitored constantly at each of the ON sideof the upper arm switch and the ON side of the lower arm switch and theaverage of two sensed values is taken as the sensed current value.Patent Document 2 also suggests, in paragraph 0021, that ringing noiseoccurs typically with opposite phases when the upper arm switch is ONand when the lower arm switch is ON. Patent Document 2 purports toenable current sensing without the influence of ringing noise.

Patent Document 1 discloses various types of current mode controlswitching regulators. However, the aim there is to provide a currentmode control switching regulator that is suitable irrespective ofwhether the ratio of the output voltage to the input voltage is low orhigh; it is not the aim to avoid the influence of ringing that occurs ina switching regulator.

Patent Document 2 suggests that ringing noise occurs during theswitching of a high-side and a low-side transistor, and that, to avoidthe influence of the ringing noise, the value of the current that passesin the upper arm switch (high-side transistor) or the lower arm switch(low-side transistor) is sensed with a current sensor in the ON periodin which whichever of the arm switches has the higher duty factor is ON.This, however, makes a duty factor calculation circuit for calculatingthe duty factor an essential constituent element, and thus requires acomplicate circuit configuration. Moreover, in this circuitconfiguration, the current sensor is implemented with a shunt resistor,and the shunt resistor is connected to the coil of the brushless motor,thus, the shunt resistor consumes electric power. In addition, the shuntresistor needs to be provided separately from the inverter circuitry,and this results in an increased circuit scale.

SUMMARY OF THE INVENTION

Devised to overcome the inconveniences mentioned above, the presentinvention aims to provide a current mode control switching regulatorthat can avoid the influence of ringing noise with a simple circuitconfiguration.

According to one aspect of the present invention, a control device thatserves as an agent for controlling a switching regulator including anoutput switch and a synchronous rectification switch includes: asummator which generates a sum sense signal by adding up a first sensesignal commensurate with the current passing in the output switch and asecond sense signal commensurate with the current passing in thesynchronous rectification switch; a smoother which generates a smoothedsense signal by smoothing the sum sense signal; and a switch driverwhich drives the output switch and the synchronous rectification switchcomplementarily through current mode control based on the smoothed sensesignal.

Other features, elements, steps, benefits, and characteristics of thepresent invention will become clearer with reference to the followingdescription of preferred embodiments thereof in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a circuit configuration diagram of an electronic deviceprovided with a current mode control switching regulator of a step-downtype (with transistors incorporated) according to a first embodiment ofthe present invention;

FIG. 1B is a circuit configuration diagram of an electronic deviceprovided with a current mode control switching regulator of a step-downtype (with transistors externally connected) according to the firstembodiment of the present invention;

FIG. 2 is a diagram showing signal waveforms at relevant nodes in FIGS.1A and 1B;

FIG. 3A is a schematic diagram showing ringing noise contained inrelevant signals and voltages when the ON duty factor of the high-sidetransistor is low in FIGS. 1A and 1B;

FIG. 3A is a schematic diagram showing ringing noise contained inrelevant signals and voltages when the ON duty factor of the high-sidetransistor is low in FIGS. 1A and 1B;

FIG. 3B is a schematic diagram showing ringing noise contained inrelevant signals and voltages when the ON duty factor of the high-sidetransistor is high in FIGS. 1A and 1B;

FIG. 4 is a diagram showing signal waveforms at relevant nodes in FIGS.1A and 1B other than the nodes shown in FIG. 2;

FIG. 5 is a signal waveform diagram illustrating the voltage and signalsoutput from a summator 8, a low-pass filter 10, and a slope signalgeneration circuit 11 which characterize the present invention;

FIG. 6A is a circuit configuration diagram of an electronic deviceprovided with a current mode control switching regulator of a step-uptype (with transistors incorporated) according to a second embodiment ofthe present invention; and

FIG. 6B is a circuit configuration diagram of an electronic deviceprovided with a current mode control switching regulator of a step-uptype (with transistors externally connected) according to the secondembodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS First Embodiment

FIGS. 1A and 1B are circuit configuration diagrams of

electronic devices provided with a current mode control switchingregulator of a step-down type according to the present invention. Inthese diagrams, components enclosed in a dash-dot-line box are to beunderstood as components integrated in a semiconductor integratedcircuit device. Embodiments of the present invention will be describedbelow with reference to the accompanying drawing. An output voltage ofan unillustrated direct-current power source such as a battery is usedas an input voltage Vin to a current mode control switching regulator 1.An input terminal IN to which the input voltage Vin is applied isconnected to the source of a high-side transistor TH1 (corresponding toan output switch). The drain of the high-side transistor TH1, aninductor L1, and the drain of a low-side transistor TL1 (correspondingto a synchronous rectification switch) are connected together at a nodeN1. The source of the low-side transistor TL is connected to a groundpotential GND. The high-side transistor TH1 and the low-side transistorTL1 function as switching transistors that turn ON and OFF repeatedlybased respectively on a high-side gate signal GH and a low-side gatesignal GL output from a PWM (pulse width modulation) control circuit 13and thereby control an inductor current Isw passed in the inductor L1.In the present description, with no regard to whether the circuit designis of a step-down or step-up type, a high-side transistor denotes onearranged on the source voltage side and a low-side transistor denotesone arranged on the ground potential GND side.

In FIGS. 1A and 1B, the high-side transistor TH1 is a p-channel MOS(metal-oxide-semiconductor) field-effect transistor (hereinafterreferred to as a pMOS transistor), and the low-side transistor TL1 is ann-channel MOS field-effect transistor (hereinafter referred to as annMOS transistor). As the high-side and low-side transistors TH1 and TL,IGBTs (insulated-gate bipolar transistors) or the like can also be used.The high-side and low-side transistors TH1 and TL1 may instead bebipolar transistors.

One end of the inductor L1 is connected to the node N1. The other end ofthe inductor L1 is connected to a node N2. To the node N2 are connectedone end of a resistor R1, one end of a smoothing capacitor C1, and anoutput terminal OUT. The other end of the smoothing capacitor C1 isgrounded. To the output terminal OUT, a load RL is connected. The loadRL is, for example, a CPU. The other end of the resistor R1 is, togetherwith one end of a resistor R2, connected to a node N3, and the other endof the resistor R2 is connected to the ground potential GND.

A feedback voltage generation circuit 2 is composed of the resistors R1and R2, which are connected in series between the node N2 and the groundpotential GND, and outputs, at the node N3, which is the connectionpoint between those resistors, a feedback voltage Vfb.

An error amplification circuit 3 compares the feedback voltage Vfb,which is fed to an inverting input terminal of the error amplificationcircuit 3, with a reference voltage Vt1, which is fed to thenon-inverting input terminal of the error amplification circuit 3, andoutputs their difference as an error signal Verr.

A phase compensation circuit 4 serves to prevent abnormal oscillation ofthe current mode control switching regulator 1. The phase compensationcircuit 4 is composed of a capacitor C2 and a resistor R3 that areconnected in series between the output terminal of the erroramplification circuit 3 and the ground terminal.

A PWM comparator 5 compares the error signal Verr, which is fed to theinverting input terminal of the PWM comparator 5, with a slope signalVsl, which is fed to the non-inverting input terminal of the PWMcomparator 5, and generates a reset signal Soff. The PWM comparator 5outputs the reset signal Soff at the time that the error signal Verrexceeds the slope signal Vsl.

A high-side amplifier 6 (corresponding to a first amplifier) comprises,for example, an operational amplifier. The difference between the inputvoltage Vin, which is fed to the source of the high-side transistor TH1,and a switching voltage Vsw, which appears at the drain of the high-sidetransistor TH1, is taken as a high-side sense voltage VH (correspondingto a first sense signal). The high-side amplifier 6 amplifies thehigh-side sense voltage VH, and outputs a high-side amplified sensevoltage VHα (corresponding to a first amplified sense signal). Thevoltage amplification factor of the high-side amplifier 6 is indicatedby the symbol α. The non-inverting input terminal of the high-sideamplifier 6 is connected to the source of the high-side transistor TH1,that is, to the input terminal IN. The inverting input terminal of thehigh-side amplifier 6 is connected to the drain of the high-sidetransistor TH1, that is, to the node N1. The high-side sense voltage VHis directly proportional to a high-side current IH that passes in thehigh-side transistor TH1. This is because, when the ON resistance of thehigh-side transistor TH1 is represented by RonH, the high-side sensevoltage VH is given by VH=RonH×IH. Accordingly, the ON resistance RonHof the high-side transistor TH1 acts as a current-voltage converter thatconverts the high-side current IH into the high-side sense voltage VH.Thus, the ON resistance RonH of the high-side transistor TH1 is utilizedas a high-side voltage sensor (corresponding to a first voltage sensor)according to the present invention. As the high-side voltage sensor, itis also possible to use, instead, a resistive element with a lowresistance value of, for example, several ohms to ten and several ohms.

The high-side amplified sense voltage VHα output from the high-sideamplifier 6 is given as the high-side sense voltage VH multiplied by thevoltage amplification factor α, that is, VH×α=RonH×IH×α. The presentinvention adopts a design in which the output of the high-side amplifier6 is extracted as a sense output current i6. The purpose is, as will beclarified later, to permit the high-side amplified sense voltage VHα anda low-side amplified sense voltage VHP to be added up by a summingresistor R4.

Like the high-side amplifier 6, a low-side amplifier 7 (corresponding toa second amplifier) comprises, for example, an operational amplifier.The source-drain voltage of the low-side transistor TL1, that is, thedifference between the ground potential GND and the switching voltageVsw, which appears at the node N1, is taken as a low-side sense voltageVL (corresponding to a second sense signal). The low-side amplifier 7amplifies the low-side sense voltage VL, and outputs a low-sideamplified sense voltage VL((corresponding to a second amplified sensesignal). The voltage amplification factor of the low-side amplifier 7 isindicated by the symbol β. The non-inverting input terminal of thelow-side amplifier 7 is connected to the ground potential GND, to whichthe source of the low-side transistor TL1 is connected. The invertinginput terminal of the low-side amplifier 7 is connected to the drain ofthe low-side transistor TL1, that is, to the node N1. The low-side sensevoltage VL is directly proportional to a low-side current IL that passesin the low-side transistor TL1. This is because, when the ON resistanceof the low-side transistor TL1 is represented by RonL, the low-sidesense voltage VL is given by VL=RonL×IL. Accordingly, the ON resistanceRonL of the low-side transistor TL1 acts as a current-voltage converterthat converts the low-side current IL into the low-side sense voltageVL. Thus, the ON resistance RonL of the low-side transistor TL1 isutilized as a low-side voltage sensor (corresponding to a second voltagesensor according to the present invention).

The low-side amplified sense voltage VLβ output from the low-sideamplifier 7 is given as the low-side sense voltage VL multiplied by thevoltage amplification factor β, that is, VL×β=RonL×IL×β. The presentinvention adopts a design in which the output of the low-side amplifier7 is extracted as a sense output current i7. The purpose is, as will beclarified later, to permit the summation of the low-side amplified sensevoltage VLβ and the high-side amplified sense voltage VLα to be carriedout easily by the summing resistor R4.

As mentioned above, the low-side amplified sense voltage VLβ output fromthe low-side amplifier 7 is given by VLβ=VL×β=RonL×IL×β, and thehigh-side amplified sense voltage VHα output from the high-sideamplifier 6 is given by VHα=VH×α=RonH×IH×α. In one embodiment accordingto the present invention, it is preferable that the equation VHα=VLβ,that is, RonH×IH×α=RonL×IL×β, be fulfilled. This makes it possible todetect ripples in the inductor current Isw.

A summator 8 (corresponding to a summator) includes the summing resistorR4. The summator 8 converts the sum current of the sense output currentsi6 and i7 into a voltage, and thereby generates a composite voltageVsense (corresponding to a sum sense signal). The composite voltageVsense thus generated by the summator 8 is a voltage that is the sum ofthe high-side and low-side amplified sense voltages VHα and VHβ. Thesense output current i6 is output from the output stage of the high-sideamplifier 6, and the sense output current i7 is output from the outputstage of the low-side amplifier 7. The sense output currents i6 and i7can be grasped as the current output signals of the high-side andlow-side amplifiers 6 and 7 respectively. The sense output currents i6and i7 are output from the output stages with high output impedances,and thus they supply the summing resistor R4 with currents thatfaithfully reflect the high-side and low-side sense voltages VH and VL.Thus, in the summing resistor R4, the high-side and low-side sensevoltages VH and VL can be added up without loss. In the summing resistorR4, after the sense output currents i6 and i7 are added up, the sumcurrent is converted back into a voltage, and thus the composite voltageVsense is generated.

A buffer 9 serves to ensure that the sum voltage Vsense output from thesummator 8 in the previous stage is delivered to a low-pass filter 10 inthe succeeding stage. The non-inverting input terminal of the buffer 9is connected to the summator 8, and is fed with the sum voltage Vsense.The non-inverting input terminal and output terminal of the buffer 9 areconnected together, and are connected to the low-pass filter 10 in thesucceeding stage. The buffer 9 outputs a buffer output voltage Vbuf. Themagnitude of the buffer output voltage Vbuf equals that of the sumvoltage Vsense.

The low-pass filter 10 (corresponding to a smoother) smooths the bufferoutput voltage Vbuf. Thus, ringing noise contained in the buffer outputvoltage Vbuf is smoothed. The low-pass filter 10 outputs a low-passfilter output voltage Vlpf (corresponding to a smoothed sense signal).The low-pass filter 10 can be configured as a well-known integratingcircuit composed of a combination of an operational amplifier, acapacitor, and a resistor. If the integrating effect of the integratingcircuit is insufficient, ringing noise is left partly uncorrected,resulting in degraded anti-ringing noise characteristics. On the otherhand, using a large CR time constant with a view to increasing theintegrating effect of the integrating circuit leads to lower response ofthe current mode control switching regulator. Thus, the time constant ofthe low-pass filter 10 is determined through a tradeoff between thosebenefits

A slope signal generation circuit 11 serves to generate the slope signalVsl, which is a triangular-wave, sawtooth-wave, or other signal that isnecessary to carry out PWM control in the current mode control switchingregulator 1. The direct-current level of the slope signal Vsl isdetermined by the low-pass filter output voltage Vlpf from the low-passfilter 10.

An oscillator 12 is configured as, for example, a well-known CRoscillator, or a circuit composed of inverters or differentialamplifiers connected in a ring. The oscillator 12 generates a set signalSon at a predetermined oscillation frequency, and feeds it to a PWMcontrol circuit 13 in the succeeding stage. The set signal Son is alsofed via a node N5 to the slope signal generation circuit 11, where itserves as a reference signal for the generation of the slope signal Vsl.

The PWM control circuit 13 receives the set signal Son, which is outputfrom the oscillator 12, and the reset signal Soff, which is output fromthe PWM comparator 5, and outputs the high-side and low-side gatesignals GH and GL, thereby to turn ON and OFF the high-side and low-sidetransistors TH1 and TL1 complementarily. The PWM control circuit 13includes an unillustrated sequential circuit, such as an RS flip-flop.To the set terminal of the RS flip-flop, the set signal Son generated bythe oscillator 12 is fed, and to the reset terminal of the RS flip-flop,the reset signal Soff output from the PWM comparator 5 is fed.

To prevent an excessive through current from passing from the high-sidetransistor TH1 to the low-side transistor TL1, the PWM control circuit13 provides a so-called dead time, that is, a period in which thehigh-side and low-side gate signals GH and GL are both at LOW level.During the dead time, the high-side and low-side transistors TH1 and TL1are both OFF, and thus cut the current path of a through current.

The PWM control circuit 13 is also furnished with a function of forciblystopping the switching operation of the switching output stages inaccordance with an unillustrated fault protection signal (a function ofturning the signals output from the high-side and low-side transistorsTH1 and TL1 to LOW level).

In FIGS. 1A and 1B, the low-side transistor TL1 operates, as asynchronous rectification transistor, in synchronism with andcomplementarily with the high-side transistor TH1. The low-sidetransistor TL1 is ON when the high-side transistor TH1 is OFF, and isOFF when the high-side transistor TH1 is ON. The low-side transistor TL1is ON when the low-side gate signal GL is at HIGH level, and is OFF whenthe low-side gate signal GL is at LOW level.

As the high-side and low-side transistors TH1 and TL1 are turned ON andOFF complementarily, the switching voltage Vsw with a square waveformappears at the node N1. The switching voltage Vsw is smoothed by theinductor L1 and the smoothing capacitor C1, so that an output voltageVout is obtained at the output terminal OUT.

In the current mode control switching regulator 1 of this configurationexample, the high-side transistor TH1, the low-side transistor TL1, theinductor L1, and the smoothing capacitor C1 together constitute aswitching output stage that steps down the input voltage Vin fed to theinput terminal IN to yield a desired output voltage Vout at the outputterminal OUT. The high-side and low-side transistors TH1 and TL1 may beincorporated in a semiconductor integrated circuit device as shown inFIG. 1A, or may be externally connected to a semiconductor integratedcircuit device as shown in FIG. 1B.

On the other hand, the error amplification circuit 3, the PWM comparator5, the slope signal generation circuit 11, the oscillator 12, and thePWM control circuit 13 are, as a switching driver that drives thehigh-side and low-side transistors TH1 and TL1 complementarily bycurrent mode control according to the low-pass filter output voltageVlpf, incorporated into the semiconductor integrated circuit device.

FIG. 2 shows the waveforms of signals at relevant nodes in the currentmode control switching regulator 1 shown in FIGS. 1A and 1B. Theswitching voltage Vsw is output to the node N1. As mentioned earlier,the switching voltage Vsw is generated by complementary operation of thehigh-side and low-side transistors TH1 and TL. For the sake ofconvenience of drawing, FIG. 2 shows an example where the duty factor isabout 65%, with the HIGH-level H period T1 longer than the LOW-level Lperiod T2. In practice, the duty factor varies with how heavy or lightthe load RL coupled to the output terminal OUT is.

In FIG. 2, the high-side current IH is the current that passes in thehigh-side transistor TH1. The high-side current IH increases graduallyduring the period in which the switching voltage Vsw is at HIGH level H.The maximum value of the high-side current IH is, for example, about 400mA. The low-side current IL is the current that passes in the low-sidetransistor TL1. The low-side current IL serves to feed a current fromthe ground potential GND side to the inductor L1 during the period inwhich the switching voltage Vsw is at LOW level L, that is, during theperiod in which the high-side transistor TH1 is OFF. The maximum valueof the low-side current IL is, like that of the high-side current IH,about 400 mA. The inductor current Isw is the current that passes in theinductor L1. The inductor current Isw is the sum current of thehigh-side and low-side currents IH and IL. The inductor current Isw hasa triangular waveform, and its amplitude value is represented by thesymbol ΔIsw. The amplitude value ΔIsw is, for example, about 100 mA. Thesum voltage Vsense is extracted from a node N4, which is the output ofthe summator 8, that is, from the summing resistor R4. The amplitudevalue ΔVsense of the sum voltage Vsense is, for example, about 1 mV,which is a very small value and is shown magnified in the drawings.

FIGS. 3A and 3B are subsidiary to FIG. 2, and schematically show stateswhere the switching voltage Vsw contains ringing noise. Ringing noiseoccurs when the high-side and low-side transistors TH1 and TL1 each turnfrom an OFF state to an ON state with opposite phases respectively.FIGS. 3A and 3B schematically show relevant voltage/signal waveforms intwo different state respectively, specifically one where the duty factorof the switching voltage Vsw output to the node N1 in FIGS. 1A and 1B iscomparatively low, for example about 10% and one where it iscomparatively high, for example about 90%.

FIG. 3A shows a case where the duty factor is low, and FIG. 3B shows acase where the duty factor is high. In FIG. 3A, the switching voltageVsw contains ringing noise nr which appears as irregular variations inamplitude width/value with the passage of time. The high-side sensevoltage VH is the drain-source voltage of the high-side transistor TH1.FIG. 3A shows how ringing noise occurs during the HIGH-level H period ofthe high-side sense voltage VH and immediately after it turns from HIGHlevel H to LOW level L. The influence of the ringing noise nr is greaterthe shorter the period T of the switching voltage Vsw, that is, thehigher its frequency.

The low-side sense voltage VL is the source-drain voltage of thelow-side transistor TL1. FIG. 3A shows how ringing noise occurs duringthe LOW-level L period of the low-side sense voltage VL and immediatelyafter it turns from LOW level L to HIGH level H. The influence of theringing noise nr is greater the shorter the period T of the switchingvoltage Vsw, that is, the higher its frequency.

In FIGS. 3A and 3B, the sum sense voltage Vsense is output to the nodeN4. The sum sense voltage Vsense is the voltage which is the sum of thehigh-side and low-side sense voltages VH and VL. In the illustratedstates, although the sum sense voltage Vsense contains slight ringingnoise, it is attenuated compared with that contained in the high-sideand low-side sense voltages VH and VL. The low-pass filter outputvoltage Vlpf is output from the low-pass filter 10, and in theillustrated states, ringing noise has been smoothed so that almost noneis contained in it. The low-pass filter output voltage Vlpf determinesthe direct-current level of the slope signal Vsl generated in the slopesignal generation circuit 11 in the succeeding stage. The slope signalVsl, which is set at a predetermined direct-current level, is comparedwith the error signal Verr in the PWM comparator 5, so that current modecontrol is carried out.

FIG. 4 shows voltages and signals other than those at the nodes shown inFIGS. 2, 3A, and 3B which have been described previously.

FIG. 4 shows, in row (a), the set signal Son output from the node N5,that is, from the oscillator 12. The set signal Son serves as a setsignal for the PWM logic circuit 13, and also serves as a referencesignal for the generation of the slope signal Vsl.

FIG. 4 shows, in row (b), the reset signal Soff output from the PWMcomparator 5. The reset signal Soff serves as a reset signal for the PWMlogic circuit 13.

FIG. 4 shows, in row (c), the switching voltage Vsw output to the nodeN1, which is the same as the switching voltage Vsw shown in FIGS. 2, 3A,and 3B but is here slightly reshaped. The switching voltage Vsw turnsfrom HIGH level H to LOW level L at a rising edge in the reset signalSoff.

FIG. 4 shows, in row (d), the buffer output voltage Vbuf output from thebuffer 9 and the low-pass filter output voltage Vlpf output from thelow-pass filter 10. The buffer output voltage Vbuf is the same as thesum sense voltage Vsense output to the node N4.

FIG. 4 shows, in row (e), the error signal Verr output from the phasecompensation circuit 4, the low-pass filter output voltage Vlpf outputfrom the low-pass filter 10, and the slope signal Vsl output from theslope signal generation circuit 11. The direct-current level of theslope signal Vsl is determined by the low-pass filter output voltageVlpf. The relationship between the direct-current levels of the slopesignal Vsl and the low-pass filter output voltage Vlpf is shown also inFIG. 5, which will be referred to later. The direct-current level of thelow-pass filter output voltage Vlpf shifts based on the magnitudes ofthe high-side current IH passing in the high-side transistor TH1 and thelow-side current IL passing in the low-side transistor TL1. Thiscontrols the direct-current level of the slope signal Vsl. Thus, in thePWM comparator 5, the level for comparison with the error signal Verrshifts, so that the current mode control switching regulator 1 operatesas such. The low-pass filter output voltage Vlpf has ringing noisesmoothed by the oscillator 12, and is thus output generally as adirect-current output voltage. At the time that the error signal Verrand the slope signal Vsl cross each other, the reset signal Soff shownin row (b) in FIG. 4 rises. The switching voltage Vsw shown in row (c)in FIG. 4 is at HIGH level H during the period in which the slope signalVsl is lower than the error signal Verr, and is at LOW level L duringthe period in which the slope signal Vsl is higher than the error signalVerr.

FIG. 5 is a signal waveform diagram illustrating the processes ofgenerating, among the relevant voltages and signals in FIGS. 1A and 1B,the composite voltage Vsense output from the summator 8, the low-passfilter output voltage Vlpf output from the low-pass filter 10, and theslope signal Vsl output from the slope signal generation circuit 11. Thegeneration of these voltages and signals involves other voltages,currents, and signals, of which some will also be described briefly withreference to FIGS. 1A and 1B.

A load current Io is the current that passes in the load RL. Asillustrated, as the load current Io, a comparatively low load currentIo1 occurs from time point t1 to time point t2, and a comparatively highload current Io2 occurs at time points t2, t3, and t4. That is, asillustrated, starting at time point t2, the load RL starts to be fedwith the comparatively high load current Io2.

The switching voltage Vsw is output from the node N1. The switchingvoltage Vsw feeds the inductor L1 with electromagnetic energy.

The switching current Isw passes in the inductor L1. As illustrated, theswitching current Isw has a sawtooth or triangular waveform, andcoordinates with the load current Io such that, at time point t2, theaverage level of the switching current Isw rises from is1 to is2.

The high-side sense voltage VH is the voltage appearing across thesource and drain of the high-side transistor TH1, and follows theswitching current Isw such that, while a comparatively low voltage VH1occurs in the period from time point t1 to time point t2, acomparatively high voltage VH2 occurs in the period from time point t3to time point t4.

The low-side sense voltage VL is the voltage appearing across the sourceand drain of the low-side transistor TL1, and, like the high-side sensevoltage VH, follows the switching current Isw such that, while acomparatively low voltage VL1 occurs in the period from time point t1 totime point t2, a comparatively high voltage VL2 occurs in the periodfrom time point t3 to time point t4.

The composite voltage Vsense is output from the summator 8. Thecomposite voltage Vsense is a voltage that is the sum of the high-sideand low-side sense voltages VH and VL. Consequently, the compositevoltage Vsense follows the switching current Isw, and exhibits generallythe same waveform as that of the switching current Isw. Accordingly, theaverage level of the composite voltage Vsense rises, at time points t2and t3, from vsel1 to vsel2.

The low-pass filter output voltage Vlpf is output from the low-passfilter 10. The low-pass filter output voltage Vlpf is a voltageresulting from the composite voltage Vsense (more precisely, the bufferoutput voltage Vbuf) having high-frequency signal components in itfiltered out by the low-pass filter 10. Practically, the low-pass filteroutput voltage Vlpf follows the shift of the composite voltage Vsense,gradually rising starting at time point t3. The low-pass filter outputvoltage Vlpf is fed to the slope signal generation circuit 11 in thesucceeding stage.

The slope signal Vsl is generated in the slope signal generation circuit11. The slope signal Vsl has a sawtooth or triangular waveform. Theslope signal Vsl is generated, for example, through the charging ordischarging of an unillustrated capacitor with a constant current. Thelevel of the lower limit of the slope signal Vsl is determined by thelow-pass filter output voltage Vlpf. Accordingly, the level of the lowerlimit of the slope signal Vsl follows the level of the low-pass filteroutput voltage Vlpf, and thus starts to rise gradually at time point t3.The slope signal Vsl is so set that there is no change between theamplitude value vsl1 from its upper to lower limit value in the periodfrom time point t1 to time point 2 and that Vsl2 after time point 3,that is, vsl1=vsl2. The relationship between the direct-current levelsof the slope signal Vsl and the low-pass filter output voltage Vlpf isshown also in row (e) in FIG. 4 previously referred to.

Second Embodiment

FIGS. 6A and 6B are circuit configuration diagrams of electronic devicesprovided with a current mode control switching regulator of a step-uptype according to the present invention. In these diagrams, componentsenclosed in a dash-dot-line box are to be understood as componentsintegrated in a semiconductor integrated circuit device. The currentmode control switching regulator 1 a of the step-up type steps up aninput voltage Vin to yield an output voltage Vout at an output terminal.In the current mode control switching regulator 1 a shown in FIGS. 6Aand 6B, to an input terminal IN to which the input voltage Vin is fed,one end of an inductor L2 is connected, and the other end of theinductor L2 is connected to the drain of a low-side transistor TL2(corresponding to an output switch). The drain of the low-sidetransistor TL2 and the source of a high-side transistor TH2(corresponding to a synchronous rectification switch) are connectedtogether. The connection point between them is a node N1. The source ofthe low-side transistor TL2 is connected to a ground potential GND. Thehigh-side transistor TH2 and the low-side transistor TL2 function asswitching transistors that turn ON and OFF repeatedly based respectivelyon a high-side gate signal GH and a low-side gate signal GL output froma PWM control circuit 13 and thereby control an inductor current Iswpassed in the inductor L2.

The high-side transistor TH2 is a pMOS transistor, and the low-sidetransistor TL2 is an nMOS transistor. As the high-side and low-sidetransistors TH2 and TL2, IGBTs or the like can also be used. Thehigh-side and low-side transistors TH2 and TL2 may instead be bipolartransistors.

In FIGS. 6A and 6B, a node N2 is connected to the output terminal OUT.To the node N2 are connected one end of a resistor R1 and one end of asmoothing capacitor C1. The other end of the smoothing capacitor C1 isconnected to a ground potential GND. To the output terminal OUT, a loadRL is connected. The load RL is, for example, a CPU. The other end ofthe resistor R1 is, together with one end of a resistor R2, connected toa node N3, and the other end of the resistor R2 is connected to theground potential GND.

A feedback voltage generation circuit 2 is composed of the resistors R1and R2, which are connected in series between the node N2 and the groundpotential GND, and outputs, at the node N3, which is the connectionpoint between those resistors, a feedback voltage Vfb. The feedbackvoltage Vfb is fed to the inverting input terminal of an erroramplification circuit 3. The non-inverting input terminal of the erroramplification circuit 3 is fed with a reference voltage Vt1. The outputterminal of the error amplification circuit 3 is connected to a phasecompensation circuit 4.

A high-side amplifier 6, like the one in FIGS. 1A and 1B, comprises, forexample, an operational amplifier, and senses a high-side current IH2that passes in the high-side transistor TH2. The high-side current IH2is sensed by sensing the voltage drop across the source and drain of thehigh-side transistor TH2. This sensing method is the same as in thecurrent mode control switching regulator 1 of the step-down type inFIGS. 1A and 1B, and accordingly no overlapping description will berepeated. A low-side amplifier 7 comprises, for example, an operationalamplifier, and senses a low-side current IL2 that passes in the low-sidetransistor TL2. The low-side current IL2 is sensed by sensing thevoltage drop across the source and drain of the low-side transistor TL2.This sensing method, too, is the same as in the current mode controlswitching regulator 1 of the step-down type in FIGS. 1A and 1B, andaccordingly no overlapping description will be repeated.

In short, the current mode control switching regulator 1 a of thestep-up type shown in FIGS. 6A and 6B differs from the current modecontrol switching regulator 1 of the step-down type shown in FIGS. 1Aand 1B in the interconnection among the input terminal IN, the high-sidetransistor TH2, the low-side transistor TL2, and the inductor L2, and inother respects both have the same circuit configuration andinterconnection; accordingly, no overlapping description will berepeated. The high-side and low-side transistors TH2 and TL2 may beincorporated in a semiconductor integrated circuit device as shown inFIG. 6A, or may be externally connected to a semiconductor integratedcircuit device as shown in FIG. 6B.

Overview:

To follow is a general description of the different embodimentsdescribed above.

A current mode control switching regulator according to oneconfiguration disclosed herein includes the following constituentelements:

(a) a switching circuit configured to convert an input voltage into apredetermined output voltage and yield the output voltage, including ahigh-side transistor and a low-side transistor,

(b) an inductor configured to be switched between storing anddischarging of energy as the switching circuit performs switchingoperation;

(c) a smoother configured to receive the energy discharged from theinductor and smooth the output voltage;

(d) an output terminal from which the output voltage extracted from thesmoothing circuit is output;

(e) an error signal voltage generation circuit configured to generate anerror signal voltage commensurate with the difference between the outputvoltage, or a feedback voltage commensurate with it, and a predeterminedreference voltage;

(f) a high-side voltage sensor and a low-side voltage sensorrespectively configured to convert currents passing in the high-side andlow-side transistors into voltages;

(g) a high-side sense voltage amplifier and a low-side sense voltageamplifier respectively configured to amplify the sense voltages outputfrom the high-side and low-side voltage sensors;

(h) a sense voltage summator configured to add up the amplified outputvoltages output from the high-side and low-side sense voltageamplifiers;

(i) a low-pass filter configured to smooth the sum voltage output fromthe sense voltage summator,

(j) a PWM comparator configured to compare the output voltage of thelow-pass filter and a slope signal and generates a PWM signal of whichthe pulse duty factor is controlled; and

(k) a PWM control circuit configured to make the high-side and low-sidetransistors perform switching operation based on the PWM output signalfrom the PWM comparator.

In a current mode control switching regulator according to anotherconfiguration disclosed herein, the high-side voltage sensor is the ONresistance of the high-side transistor, and the low-side voltage sensoris the ON resistance of the low-side transistor.

In a current mode control switching regulator according to anotherconfiguration disclosed herein, when the current that passes in thehigh-side transistor is represented by IH, the ON resistance of thehigh-side transistor is represented by RonH, the voltage amplificationfactor of the high-side sense voltage amplifier is represented by a, thecurrent that passes in the low-side transistor is represented by IL, theON resistance of the low-side transistor is represented by RonL, and thevoltage amplification factor of the low-side sense voltage amplifier isrepresented by P, then the equation IH×RonH×α=IL×RonL×β is fulfilled.

In a current mode control switching regulator according to anotherconfiguration disclosed herein, the voltages amplified by the high-sideand low-side amplifiers are converted into currents and are outputrespectively from the output stages of the high-side and low-sideamplifiers.

In a current mode control switching regulator according to anotherconfiguration disclosed herein, the summator includes a summing resistorthat is coupled with the output stages of the high-side and low-sideamplifiers.

In a current mode control switching regulator according to anotherconfiguration disclosed herein, the sum signal is applied via a bufferto the low-pass filter.

According to the various embodiments disclosed herein, despite acomparatively simple circuit configuration, the ringing noise thatoccurs when the high-side and low-side transistors respectively turn ONand OFF is added up, and while the sum of the noise components issuppressed with the low-pass filter, the current mode control switchingregulator is controlled. Thus, it is possible to provide a current modecontrol switching regulator that avoids the influence of ringing noise.

INDUSTRIAL APPLICABILITY

As will be clear from what has been discussed above, despite its simplecircuit configuration, a current mode control switching regulatoraccording to the present invention can eliminate the influence ofringing noise, and boasts high industrial applicability.

What is claimed is:
 1. A control device that serves as an agent forcontrolling a switching regulator including an output switch and asynchronous rectification switch, the control device comprising: asummator configured to generate a sum sense signal by adding up a firstsense signal commensurate with a current passing in the output switchand a second sense signal commensurate with a current passing in thesynchronous rectification switch; a smoother configured to generate asmoothed sense signal by smoothing the sum sense signal; and a switchdriver configured to drive the output switch and the synchronousrectification switch complementarily through current mode control basedon the smoothed sense signal.
 2. The control device according to claim1, further comprising: a first amplifier configured to generate a firstamplified sense signal by amplifying the first sense signal; and asecond amplifier configured to generate a second amplified sense signalby amplifying the second sense signal, wherein the summator generatesthe sum sense signal by adding up the first and second amplified sensesignals.
 3. The control device according to claim 2, wherein the firstand second amplified sense signals are both current signals.
 4. Thecontrol device according to claim 2, wherein the summator includes asumming resistor configured to generate the sum sense signal byconverting a sum current of the first and second amplified sensesignals. into a voltage.
 5. The control device according to claim 1,further comprising: a buffer configured to feed the sum sense signal tothe smoother.
 6. The control device according to claim 1, wherein thesmoother is a low-pass filter.
 7. The control device according to claim1, wherein the switch driver includes: an oscillator configured togenerate a set signal at a predetermined oscillation frequency; an erroramplification circuit configured to generate an error signalcommensurate with a difference between an output voltage of theswitching regulator, or a feedback voltage commensurate therewith, and apredetermined reference voltage; a slope signal generation circuitconfigured to generate a slope signal commensurate with the smoothedsense signal; a PWM (pulse width modulation) comparator configured togenerate a reset signal by comparing the slope signal with the errorsignal; and a PWM control circuit configured to generate driving signalsfor the output switch and the synchronous rectification switchrespectively based on the set signal and the reset signal.
 8. Thecontrol device according to claim 7, wherein a phase compensationcircuit is connected to an output terminal of the error amplificationcircuit.
 9. A switching regulator comprising: a switching output stageconfigured to convert an input voltage into a predetermined outputvoltage and output the output voltage, the switching output stageincluding the output switch and the synchronous rectification switch;and the control device according to claim 1, the control devicecontrolling driving of the switching output stage.
 10. The switchingregulator according to claim 9, wherein the switching output stagefurther includes: an inductor configured to be switched between storingand discharging of energy as the output switch and the synchronousrectification switch perform switching operation; and a smootherconfigured to smooth the output voltage by receiving the energydischarged from the inductor.
 11. The switching regulator according toclaim 9, further comprising: a first current sensor and a second currentsensor configured to generate the first and second sense signalsrespectively by sensing individually the currents passing in the outputswitch and the synchronous rectification switch.
 12. The switchingregulator according to claim 11, wherein the first current sensor is anON resistance of the output switch, and the second current sensor is anON resistance of the synchronous rectification switch.
 13. The switchingregulator according to claim 9, wherein let a current passing in theoutput switch be IH, let the ON resistance of the output switch be RonH,let an amplification factor of the first amplifier which amplifies thefirst sense signal be α, let a current passing in the synchronousrectification switch be IL, let the ON resistance of the synchronousrectification switch be RonL, and let an amplification factor of thesecond amplifier which amplifies the second sense signal be β, then anequation IH×RonH×α=IL×RonL×β is fulfilled.
 14. The switching regulatoraccording to claim 9, wherein the output voltage is lower than the inputvoltage.
 15. The switching regulator according to claim 14, wherein theoutput switch is a p-channel MOS (metal-oxide-semiconductor)field-effect transistor, and the synchronous rectification switch is ann-channel MOS field-effect transistor.
 16. The switching regulatoraccording to claim 9, wherein the output voltage is higher than theinput voltage.
 17. The switching regulator according to claim 16,wherein the output switch is an n-channel MOS(metal-oxide-semiconductor) field-effect transistor, and the synchronousrectification switch is a p-channel MOS field-effect transistor.
 18. Theswitching regulator according to claim 9, wherein the output switch andthe synchronous rectification switch are incorporated in a semiconductorintegrated circuit device in which the control device is integrated. 19.The switching regulator according to claim 9, wherein the output switchand the synchronous rectification switch are externally connected to asemiconductor integrated circuit device in which the control device isintegrated.
 20. An electronic device comprising: the switching regulatoraccording to claim 9; and a load configured to receive electric powerfrom the switching regulator.